1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device (substrate structure) by which warpage thereof is adjustable.
Priority is claimed on Japanese Patent Application No. 2010-034842, filed Feb. 19, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
As a substrate structure including a rear electrode penetrating through a substrate (hereinafter, “penetrating electrode”), there have been a wiring board including multiple insulating layers (such as resin layers) over a substrate, a semiconductor device including semiconductor integrated circuits on a semiconductor substrate (such as a semiconductor chip), and the like.
Such a semiconductor device is electrically connected to a semiconductor integrated circuit, and includes a surface electrode electrically connected to the penetrating electrode. When another substrate structure (such as a wiring board or another semiconductor device) is stacked onto the semiconductor device, the substrate structure is connected to the surface electrode or the penetrating electrode.
Regarding the above semiconductor device, semiconductor integrated circuits are formed only on a surface of the semiconductor substrate. For this reason, warpage of the semiconductor device occurs due to the difference in internal stress or thermal expansion coefficient between multiple insulating layers and wiring patterns, which form the semiconductor integrated circuits, and the semiconductor substrate.
Particularly when the vertical size of the semiconductor device is reduced, i.e., when a vertical thickness of a semiconductor substrate is reduced (to, for example, 50 nm), warpage of the semiconductor device is likely to occur. When another substrate structure, such as a wiring board or another semiconductor device, is mounted on the warped semiconductor device, the reliability of electrical connection between the semiconductor device and the substrate structure degrades.
To decrease warpage of the semiconductor device, according to a method disclosed by Japanese Patent Laid-Open Publication No. 2005-158929, multiple semiconductor integrated circuits are formed on a semiconductor wafer. Then, a thickness of a semiconductor substrate is reduced. Then, a metal layer covering a rear surface of the semiconductor substrate is formed as an element for reducing warpage.
According to a method disclosed by Japanese Patent Laid-Open Publication No. 2005-310817, a process of forming an insulating layer covering a rear surface of a semiconductor substrate is additionally provided to reduce warpage of the semiconductor device.
In any case, it is necessary to carry out an additional process of forming a metal layer or an insulating layer that covers a rear surface of the semiconductor substrate to reduce the warpage of the semiconductor device, thereby increasing the number of processes, and therefore causing an increase in manufacturing cost.
The above problem also arises when such a metal layer or an insulating layer is formed on a wiring board including a resin board (such as a glass epoxy board), a ceramic board, or the like. The above problem also arises when an electrode other than a penetrating electrode is provided on a rear surface of a wiring board.